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Freescale Semiconductor /MK61F15WS /DDR /CR44

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Interpret as CR44

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0P2TYP 0RESERVED0 (0)WRRLAT 0RESERVED0 (0)WRRSHARE 0RESERVED0WRRERR0RESERVED

WRRLAT=0, WRRSHARE=0

Description

DDR Control Register 44

Fields

P2TYP

Port 2 Type
RESERVED

Reserved
WRRLAT

WRR Latency

0 (0): Free-running

1 (1): Limited
RESERVED

Reserved
WRRSHARE

WRR Shared arbitration

0 (0): Port 0 and port 1 are treated independently for arbitration

1 (1): Port 0 and port 1 are grouped together for arbitration
RESERVED

Reserved
WRRERR

WRR parameters Error
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data